An analog-digital converter is an electronic circuit allowing an analog signal, for example, an electrical voltage, to be converted into a digital signal coded over one or more bits.
In order to convert an analog signal into a digital signal, one solution consists in generating a voltage ramp (for example, a rising voltage ramp) by means of a digital-analog converter whose dynamic range is known, starting a counter when the value of the voltage ramp is equal to the value of the analog signal, and stopping the counter when the ramp reaches its maximum value.
In order to obtain the value of the digital signal, the counter may for example, be configured for counting down from an initial value corresponding to the maximum value of the ramp. The value of the counter when it is stopped then represents the value of the analog signal.
FIG. 1 illustrates a timing diagram representing two possible time variations of the counter during an analog-digital conversion conforming to this solution.
The analog-digital conversion here is timed by a clock signal CLK.
At an initial time to, a voltage ramp RMP is generated and a first analog signal SIG1 to be converted is acquired.
At a first time t1, the value of the first analog signal SIG1 and the value of the ramp are equal. A first counter signal CNT1 equal to the clock signal CLK is then generated.
At a second time t2, the ramp RMP reaches its maximum value, hence the conversion is halted and the signals RMP, CLK and CNT1 go into the low state.
The counter signal CNT1 is delivered to an asynchronous counter. The value of the least significant bit varies at the cadence of the edges of the signal CNT1. Thus, the value of the digital signal is equal to the number of edges of the first counter signal CNT1.
Moreover, since the counter signal CNT1 is equal to the clock signal CLK between the times t1 and t2, the digital value of the analog signal SIG1 is indeed equal to the number of edges of the clock signal having occurred between the first time t1 and the second time t2, in other words here six.
However, if the same process is carried out with a second analog signal SIG2 whose value differs slightly from that of the first signal, in other words here with a signal SIG2 whose value is very slightly higher than the value of the first signal SIG1, the equality of the second signal and the ramp occurs a little later, at a third time t1′.
A second counter signal CNT2 equal to the clock signal CLK is generated, and as the equality has occurred during a high state of the clock signal CLK, the counter CNT2 begins with an additional rising edge F.
Thus, between the times t1′ and t2, the number of edges of the clock signal CLK is less than the number of edges of the second counter signal CNT2. The digital value will not therefore be representative of the analog signal because it will not be equal to the number of edges of the clock signal having taken place between the time t1′ and t2.
In other words, owing to the additional rising edge F generated by the counter when the equality occurs during a high state of the clock, the counter is only able to count in two's. The value of the least significant bit of the digital value is therefore not significant.
One solution would consist in not taking into account the least significant bit. However, this divides the rate of the counter by two, and hence requires a clock generator with twice the frequency to compensate for this.